Field of the Invention
The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer.
Description of the Related Technology
The semiconductor industry is on an ongoing quest to integrate more functionality into a smaller form factor while increasing performance, lowering power consumption and/or reducing cost. Traditionally, two-dimensional and lateral scaling approaches have been predominantly used, including, for example, conventional CMOS scaling, including multiple IP cores in a single die (system-on-chip (SoC)), including multiple dies in a single package (multi-chip package (MCP)) and including multiple ICs on a printed circuit board (PCB). More recently, three dimensional scaling including scaling in the third, vertical dimension started to become exploited, including, for example, system-in-package (SiP), in which multiple naked dies are vertically stacked in a single IC package, and interconnected by means of wire-bonds to the substrate, and package-on-package (PoP), in which multiple packaged chips are vertically stacked.
In particular, three-dimensional (3D) stacking of chips is gaining increased interest, as it promises higher transistor densities and smaller footprints of electronic products. The latest evolution in this list of innovations is the so-called three-dimensional stacked IC (3D-SIC), which includes a single package containing a vertical stack of naked dies which are interconnected by means of inter-die interconnections, and can further include through-substrate-vias (TSVs). 3D stacking based on inter-die interconnections offers the benefits of more functionality, higher bandwidth and performance at smaller sizes, alongside lower power consumption and cost; and this even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive.
Currently, a lot of research and development work is done around three-dimensional stacking of integrated circuits. Two popular set-ups are illustrated in FIG. 1(a) and FIG. 1(b). FIG. 1(a) illustrates an interposer-based 3D die stack in which multiple active dies 10, 11, 12 are placed side-by-side on top of and interconnected through an interposer 13, such as a semiconductor, e.g. silicon, interposer. The active dies 10, 11, 12 are typically connected to the interposer 13 by means of high-density micro-bumps 14, e.g. Cu and CuSn micro-bumps. In a typical set-up (as depicted in FIG. 1(a)), the interposer contains TSVs 15 that connect to external package pins. Such 3D stacks are attractive for high-performance compute and communication applications, as they offer high-bandwidth interconnect between various active dies 10, 11, 12 and good cooling opportunities. Also, such 3D stacks allow to break up a single large die into multiple dies 10, 11, 12 and hence increase the yield, and enable the combination of heterogeneous dies in a single product. It can be predicted that interposer-based 3D stacking with multiple active dies 10, 11, 12 placed side-by-side on top of and interconnected through an interposer 13 will evolve to 3D stacking, where multiple 3D towers 16, 17 of active dies are placed side-by-side of top of and interconnected through an interposer, for example a semiconductor interposer such as a silicon interposer, as for example illustrated in FIG. 1(b). Such 3D stacks are attractive also for hand-held and portable consumer electronics, due to their small footprint.
In order to reduce the overall system cost, there is a need to reduce the cost of fabricating the interposer 13. Typically, a low-cost process technology is used to fabricate such interposer 13 which can use: relatively larger feature sizes, predominantly passive components (i.e., minimum active components), mature process technologies, and high-yielding manufacturing processes.
Despite the high yield, it typically pays off to perform pre-bond testing of the interposer 13 before stacking. This is mainly driven by the cost ratio between the (cheap) interposer die 13 and the (more expensive) active dies 10, 11, 12 or die towers 16, 17 placed on top of it. If a faulty interposer 13 is detected only after stacking active dies 10, 11, 12 or die towers 16, 17 on top of it, the entire stack needs to be discarded, and in this way, “a 10¢ interposer can ‘kill’ two 50$ dies”. Hence, there is a need for pre-bond (“Known-Good Die”, KGD) testing of interposers 13 for manufacturing defects.
Testing an interposer which predominantly comprises passive components may not be conceptually very difficult. Nevertheless, testing the interposer can be practically difficult at least in part because of difficulty of accessing internal components of the interposer, e.g., interconnects, to be tested. For example, conventionally, testing an interconnect is typically performed by accessing both ends of the interconnect. To test horizontal interconnects in an interposer, the interconnects can be accessed from the top. However, the microbumps 14 at the top can be fine-pitched, for example, making it difficult to access the interconnects via a probe card. In addition, a suitable probe card may be expensive and/or introduce inaccuracies in touch-down. There might also be many interconnect ends to be probed, spread out over a large area. Moreover, ideally, probes would be placed at top and bottom of the interposer, to test signal paths from top to bottom of the interposer and vice versa. However, it is difficult to get such dual side access, as typically a wafer will be present on a chuck, thus reducing the access possibilities to single side access. Dual side probing on a thinned wafer poses yet more problems, in view of deformation of the thinned wafer which will occur (sagging, warping, etc.). Thus, there is a need for testing methods that can overcome the challenges associated with accessing internal components, e.g., interconnects, of a semiconductor die, such as an interposer,